Thin-Body SOI Capacitorless DRAM Cell Design Optimization and Scaling

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. Acknowledgement I would like to offer my deepest thanks to my academic advisor, Professor Tsu-Jae King Liu, whose unflinching intellect guided my research and writing from start to finish. I am equally grateful to Professors to thank several former, current students, and all the members of the UC Berkeley who gave me valuable feedback. I owe a great deal of thanks to Samsung Electronics (colleagues and supervisors) for their financial support. Finally I owe my gracious thanks to my family. In particular, I want to acknowledge my lovely spouse, Ji Hye Yi, and our adorable sons HyunSung Cho and HyunSoo Cho. Capacitorless dynamic random access memory (DRAM) is a promising solution to cell-area scalability and complex fabrication process issues for conventional DRAM. The thin body SOI transistor, which suppresses the short channel effect and also minimizes variability, is selected for the capacitorless DRAM cell structure. The impact of substrate doping concentration on capacitorless DRAM cell performance is studied and a novel selective well structure is proposed. A capacitorless DRAM cell design with BJT-based operation (BJT mode) is known to have larger sensing margins and longer retention times. Controlling band-to-band tunneling leakage (BTBT) related to the electric field plays a key role in limiting retention time. In the BJT mode, BTBT in the Hold 0 state limits data retention time (D0 failure). By optimizing the underlap between the front gate and the source/drain regions as well as the operating voltages, retention time exceeding 1 second should be attainable for a cell with 25 nm gate length. The scaling limits of optimized capacitorless DRAM cells are also investigated through the analysis of variations. Signal sense margin analysis indicates that the ultimate scaling limit is 13 nm (gate length) for embedded DRAM applications and 16.5 nm for stand-alone DRAM applications. The positive feedback MOSFET (PF-FET) was fabricated on thin body (10 nm) and UTBOX (10 nm) SOI structure. Positive feedback occurs as a result of both the BJT operation and the floating body effect from …